1. Field of the Invention
This invention generally relates to semiconductor device manufacturing, and more particularly, the invention relates to a method of fabricating semiconductor devices having a reduced carrier-depletion effect of polysilicon (polySi) gate conductor. Even more specifically, the invention relates to the use of a fat disposable spacer, in such fabrication methods, to facilitate post-doping of the polySi gate conductor without disturbing the optimum source and drain doping profile for a high performance metal oxide semiconductor filed effect transistor (MOSFET).
2. Background Art
With decreasing gate lengths in metal oxide semiconductor field effect transistors (MOSFETs), the effective gate dielectric thicknesses (Tinv) of the order of 2 nm or less are required to improve short-channel behavior and to increase the on-current without increasing the off-current. The contribution of carrier-depletion effect of the polySi gate conductor at the gate dielectric interface, the so called “polySi depletion effect,” to the effective gate dielectric thickness becomes significantly large when the Tinv is of the order of 2 nm or less. It has been recognized that it is important to dope the polySi gate heavily, particularly near the gate dielectric interface, to reduce the polySi depletion effect. However, with the conventional manufacturing process, where the gate polySi and S/D diffusion are implanted at the same time, it is not possible to dope the polySi gate in such a way to minimize the polySi depletion effect without compromising the optimum source and drain (S/D) diffusion doping profile, because the polySi and S/D diffusion are doped by the same ion implantations. It is desirable to decouple the PolySi and S/D implantation so that they can be optimized separately.
One method to decouple the gate and S/D implant is known as “pre-doping” of PolySi. The polySi is implanted prior to PolySi etching to define the gate conductor to boost polySi-doping levels. The disadvantage of this method is that the PFET and NFET areas are doped using different species (e.g., boron and arsenic) which can cause these areas to etch differently during the PolySi etch. This is a serious concern for device length control of both NFET and PFET.
Another method to decouple the gate that has been used is known as post-doping with “anti-spacer.” It is called post-doping because the additional doping to the gate is made after the gate PolySi etching to avoid the problems associated with etching of the dual doped PolySi. With the post-doping method with anti-spacer, a planarizing polymer layer such as an anti-reflective coating material (ARC) is spun onto the wafer after the PolySi has been etched. The ARC fills areas between the PolySi lines, which blocks the implant from going into the Si S/D regions while thin enough ARC is left on top of the PolySi. However, the most serious drawback of this technique is that enough ARC material actually stays on top of the PolySi of either a wide PolySi line or dense multiple PolySi lines, which blocks the implant from going into the PolySi, where it is needed.